This invention relates generally to electronic circuitry and more particularly to digital-to-analog converters.
Digital-to-analog (D/A) converters are used to convert digital data to an analog equivalent. For example, a D/A converter for a video board of a personal computer (PC) will convert digital video data generated by the PC into analog signals which can drive a video display. Since modern color video displays can display hundreds or even thousands of hues and intensities, it is important that the D/A conversion be very accurate to avoid errors in the displayed image.
In FIG. 1, a prior art video D/A converter 10 is shown which may be advantageously implemented in complementary metal oxide semiconductor (CMOS) technology. The D/A converter 10 includes a decoder 12, an array 14 of current cells 16, and a bias generator 18. Digital data from a data bus 20 is applied to decoder 12 which selectively activates one or more current cells 16 to produce an analog signal on analog output line 22.
Each of the current cells 16 includes a current source MOSFET (metal oxide semiconductor field effect transistor) 24 and two switch MOSFETS 26 and 28. MOSFETS 24, 26 and 28 are all p-channel devices. The source of MOSFET 24 is coupled to the V.sub.dd terminal of a power supply and its gate is coupled to a bias line 30. The sources of MOSFETS 26 and 28 are coupled to the drain of MOSFET 24, the drain of MOSFET 26 is coupled to ground, and the drain of MOSFET 28 is coupled to analog output line 22.
The number n of cells 16 is related to the number of bits b in data bus 20 by the relationship n=2.sup.b. If, for example, the data bus 20 is 4 bits wide, there will be n=2.sup.4 =16 of the current cells 16.
The gate of MOSFET 26 of each current cell 16 is coupled to the output of decoder 12 by a line A and the gate of MOSFET 28 of each current cell 16 is coupled to line A by an inverter 32. The line A a first current cell 16 is labelled A.sub.1 while the line A of the n.sup.th current cell 16 is labelled A.sub.n. When the decoder 12 applies a low voltage (LO) signal to a line A, the MOSFET 26 will turn on and MOSFET 28 will turn off with the result that the current provided by MOSFET 24 will flow to ground. When a high voltage (HI) signal is applied to a line A, the MOSFET 26 will turn off and the MOSFET 28 will turn on, resulting in a current will flowing through output line 22 and a resistor R.sub.load to ground. As will be discussed in greater detail subsequently, the number of current cells which are activated at any one time correspond to the numeric value of the datum on data bus 20.
Bias generator 18 produces a bias voltage on bias line 30 which controls the current sources 24 of the current cells 16. This prior art bias generator 18 includes an operational amplifier (opamp) 34, a p-channel MOSFET 36, and a resistor R.sub.ref. One input of the opamp 34 is coupled to an external reference voltage V.sub.ref and the other input of opamp 34 is coupled to bias line 30. The source of MOSFET 36 is coupled to V.sub.dd, its drain is coupled to bias line 30, and its gate is coupled to the output of opamp 34. R.sub.ref is coupled between bias line 30 and ground.
As long as V.sub.dd and V.sub.ref are stable, the bias generator 18 serves to provide a substantially constant voltage equal to V.sub.ref on bias line 30. If the voltage on bias line 30 rises above V.sub.ref, the positive input to opamp 34 is greater than the negative input, causing the output of opamp 34 to become more positive and thereby reducing the current I.sub.ref flowing through MOSFET 36 and pulling down the voltage on bias line 30 to V.sub.ref. If the voltage on bias line 30 falls below V.sub.ref, the positive input to opamp 34 is less than the negative input, causing the output of opamp 34 to increase the current I.sub.ref flowing through MOSFET 36 and thereby pulling up the voltage on bias line 30 to V.sub.ref.
The ideal performance of a MOSFET 24 of a current cell 16 is illustrated in FIG. 2a. When the power supply voltage V.sub.dd is zero, the current I.sub.c is also zero. The current I.sub.c then rises substantially linearly until V.sub.dd reaches a threshold voltage V.sub.dsat at which time I.sub.c becomes a constant. In other words, I.sub.c is ideally independent of V.sub.dd as long as V.sub.dd is greater than the threshold voltage V.sub.dsat of the MOSFET 24. Therefore, if V.sub.dd is chosen to be sufficiently greater than V.sub.dsat, minor variations in the power supply voltage will not, in theory, effect the output of the MOSFET 24.
While the performance of MOSFET 24 approaches the ideal depicted in FIG. 2a, its performance is more realistically depicted in the graph of FIG. 2b. Again there is a substantially linear relationship between V.sub.dd and I.sub.c between 0&lt;V.sub.dd &lt;V.sub.dsat. However, at voltages V.sub.dd &gt;V.sub.dsat the current I.sub.c through MOSFET 24 increases substantially linearly with increasing V.sub.dd, albeit at a lesser rate than when V.sub.dd is less than V.sub.dsat. In consequence, a voltage variation v in V.sub.dd will result in an error current e in I.sub.c. Since the outputs of all of the current cells 16 are coupled together in parallel, this will result in a cumulative error current E=e2.sup.b, which can be quite substantial.
A prior art solution to this problem is to provide a cascode current source comprising two rather large MOSFETS coupled in series. While this solution does reduce errors caused by voltage variations in the source, it comes at the price of increasing the device count and real-estate usage of the circuit, and tends to slow the operation of the circuit.